Today's Flash memory devices store information with high density on Flash cells with ever smaller dimensions. In addition, Multi-Level Cells (MLC) store several bits per cell by setting the amount of charge in the cell. Flash devices are organized into (physical) pages. Each page contains a section allocated for data (512 bytes-8 Kbytes) and a small amount of spare bytes (16-32 or more bytes for every 512 data bytes) containing redundancy and back pointers. The redundancy bytes are used to store error correcting information, for correcting errors which may have occurred during the page Read. Each Program operation is performed on an entire page. A number of pages are grouped together to form an Erase Block (erase block). A page cannot be erased unless the entire erase block which contains it is erased.
One common application of Flash devices is SD cards. An SD card will typically contain Flash devices and a controller. The controller translates commands coming in through the SD interface into actions (Read/Write/Erase) on the Flash devices. The most common SD commands will be Read and Write sector commands where a sector is a sequence of 512 bytes. The read or write commands may be of a single sector or multiple sectors. These commands refer to logical addresses. These addresses can then be redirected to new addresses on the FLASH memory which need not directly correspond to the logical addresses. This is due to memory management carried out by the controller in order to support several features such as wear-leveling, bad block management, firmware code and data, error-correction, and more.
Due to the small dimensions and the price limitations on the card, the controller will typically have only a small RAM. This limits the type of memory management which will be carried out by the controller. The controller will typically manage the memory at the erase block level. That is, the logical memory space will be divided into units of memory contained within a single erase block (or some constant multiple of erase blocks) such that all logical sector addresses will be mapped to the same erase block. This requires that the controller will only hold an erase block allocation map rather than a sector allocation map (or some unit smaller than an erase block). This allows the controller to use only a small amount of memory for the purpose of management.
However, this type of management has the drawback that for random sector writes (or memory units smaller than an erase block), erase blocks must be frequently rewritten. To understand why consider that each new piece of information must be written into an empty page (in Flash memories a page may not be rewritten before the entire block is erased first).
If only a portion of the memory unit contained within an erase block is rewritten, it is written into a freshly allocated, erased erase block. The remaining, unmodified, content of the erase block must then be copied into the new erase block and the former erase-block is declared as free and erased. This operation is referred to as “sealing” or “merging”. This includes collecting the most recent data of a logical block and merging it with the rest of the block data in a single erase block. Thus, even if only a single sector from an erase block is rewritten, a complete erase block must be rewritten. Apart from causing a significant degradation in the average write speed, it also imposes a significant delay in the response time between random write sector operations.
The SD 2.0 specification does not help as it also puts a limit on the write-time of a single sector (smaller than 250 mS). This may not be a problem if the page write time is short or the number of pages per block is small. For example, in a 2 bits per cell MLC Flash device there will typically be 128 pages per block and the page program will typically be around 1 ms. Therefore, the delay induced by a single random write operation will take around 130-150 mS.
However, in a 3 bit per cell device which has 192 pages per block and each page takes longer to program, a block merging operation is likely to require more than 250 mS.
There is therefore a need for a system and device that allows keeping pace with the incoming random sector write requests, regardless of the number of requests, without violating timing constraints such as the 250 mS time limit on each write sector operation.